View ADG1436_1108396.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Preliminary Technical Data
FEATURES
2 Max On Resistance 0.5 Max On Resistance Flatness 200mA continious current 33 V supply range Fully specified at +12 V, 15 V, 5 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 16-lead TSSOP and 16-lead LFCSP packages
2 Max On Resistance, 15 V/12 V/5 V iCMOSTM Dual SPDT Switch ADG1436
FUNCTIONAL BLOCK DIAGRAM
ADG1436
S1A D1 S1B IN1 IN2 S2A D2 S2B
APPLICATIONS
Automatic test equipment Data aquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Communication systems Relay Replacement
SWITCHES SHOWN FOR A LOGIC "1" INPUT
Figure 1.TSSOP package
ADG1436
S1A D1 S1B S2A D2 S2B
LOGIC
IN1
IN2
EN
SWITCHES SHOWN FOR A "1" INPUT LOGIC
Figure 2.LFCSP package
GENERAL DESCRIPTION
The ADG1436 is a monolithic CMOS device containing two independently selectable SPDT switches. An EN input on the LFCSP package is used to enable or disable the device. When disabled, all channels are switched off. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. Both switches exhibit break-before-make switching action for use in multiplexer applications. It is designed on an iCMOS process. iCMOS (industrialCMOS) is a modular manufacturing process combining high voltage CMOS (complementary metal-oxide semiconductor) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
voltages, while providing increased performance, dramatically lower power consumption, and reduced package size. The on resistance profile is very flat over the full analog input range ensuring excellent linearity and low distortion when switching audio signals. iCMOS construction ensures ultralow power dissipation, making the part ideally suited for portable and battery-powered instruments.
PRODUCT HIGHLIGHTS
1. 2. 3. 4. 5. 6. 2 Max On Resistance over temperature. Minimum distortion 3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V. No VL logic power supply required. Ultralow power dissipation: <0.03 W. 16-lead TSSOP and 16-lead 4 mm x 4mm LFCSP packages.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2007 Analog Devices, Inc. All rights reserved.
ADG1436 TABLE OF CONTENTS
Specifications..................................................................................... 3 Dual Supply ................................................................................... 3 Single Supply ................................................................................. 4 Absolute Maximum Ratings............................................................ 7 Truth Table For Switches ............................................................. 8 ESD Caution.................................................................................. 7
Preliminary Technical Data
Pin Configurations and Function Descriptions ............................8 Terminology .......................................................................................9 Typical Performance Characteristics ........................................... 10 Test Circuits..................................................................................... 13 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15
REVISION HISTORY
Rev. PrC | Page 2 of 17
Preliminary Technical Data SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V 10%, VSS = -15 V 10%, GND = 0 V, unless otherwise noted. Table 1.
25C ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match between Channels (RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 Transition Time, tTRANS
tON (EN) tOFF (EN)
ADG1436
-40C to +85C
-40C to +125C VDD to VSS V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max
ns typ ns max ns typ ns max
1.5 2 0.1 0.5 0.1 0.5 0.01 0.5 0.01 0.5 0.04 1
VS = 10 V, IS = -10 mA; Figure 23 VDD = +13.5 V, VSS = -13.5 V VS = 10 V, IS = -10 mA
VS = -5 V/0 V/+5 V; IS = -10 mA VDD = +16.5 V, VSS = -16.5 V VS = 10 V, Vs = 10 V; Figure 23 VS = 10 V, Vs = 10 V;; Figure 23 VS = VD = 10 V; Figure 23
2.5 2.5 2.5
5 5 5 2.0 0.8
0.005 0.5 5 120 150
85 105 105 125 130 150
VIN = VINL or VINH
200
140 170
RL = 300 , CL = 35 pF VS = +10 V; Figure 25
RL = 300 , CL = 35 pF VS = 10 V; see Figure 25 RL = 300 , CL = 35 pF VS = 10 V; see Figure 25
Break-before-Make Time Delay, tD Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD IDD ISS
15 50 50 60 0.015 100 35 35 70 0.001
40 1
ns typ ns min pC typ dB typ dB typ % typ MHz typ pF typ pF typ pF typ A typ A max A typ A max A typ A max
RL = 300 , CL = 35 pF VS1 = VS2 = +10 V; Figure 27 VS = 0 V, RS = 0 , CL = 1 nF; Figure 29 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 30 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 31 RL = 110, 5 V rms, f = 20 Hz to 20 kHz RL = 50 , CL = 5 pF; Figure 32 f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V VDD = +16.5 V, VSS = -16.5 V Digital Inputs = 0 V or VDD Digital Input = 5 V Digital Inputs = 0 V, 5V or VDD
1 150 300 0.001 1.0
Rev. PrC| Page 3 of 17
ADG1436
25C
VDD/VSS
Preliminary Technical Data
-40C to +85C -40C to +125C
4.5/16.5 V min/max Gnd = 0V
1
Guaranteed by design, not subject to production test.
SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2.
25C ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match between Channels (RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 Transition Time, tTRANS
tON (EN) tOFF (EN)
-40C to +85C
-40C to +125C 0 V to VDD V typ max typ max typ
2.5 3 0.1
VS = +10 V, IS = -10 mA; Figure 23 VS = +10 V, IS = -10 mA
4
0.5 0.1 0.5 0.01 0.5 0.01 0.5 0.04 1
VS = +3 V/+6 V/+9 V, IS = -10 mA VDD = 12 V VS = 1 V/10 V, VD = 10 V/1 V; Figure 24 VS = 1 V/10 V, VD = 10 V/1 V; Figure 24 VS = VD = 1 V or 10 V, Figure 25
2.5 2.5 2.5
5 5 5 2.0 0.8
nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max
ns typ ns max ns typ ns max
0.001 0.5 5 120 150
85 105 105 125 130 150
VIN = VINL or VINH
200
140 170
Break-before-Make Time Delay, tD Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth CS (Off) CD (Off) CD, CS (On)
15 1 30 50 60 0.015 100 35 35 70
ns typ ns min pC typ dB typ dB typ % typ MHz typ pF typ pF typ pF typ
RL = 300 , CL = 35 pF VS = 8 V; Figure 25 RL = 300 , CL = 35 pF VS = 8 V; Figure 25 RL = 300 , CL = 35 pF VS = 8 V; Figure 25 RL = 300 , CL = 35 pF VS1 = VS2 = 8 V; Figure 27 VS = 6 V, RS = 0 , CL = 1 nF; Figure 29 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 30; RL = 50 , CL = 5 pF, f = 1 MHz; Figure 31 RL = 110, 5 V rms, f = 20 Hz to 20 kHz RL = 50 , CL = 5 pF; Figure 32 f = 1 MHz; VS = 6V f = 1 MHz; VS = 6V f = 1 MHz; VS = 6 V
Rev. PrC | Page 4 of 17
Preliminary Technical Data
25C POWER REQUIREMENTS IDD IDD
VDD
ADG1436
-40C to +85C -40C to +125C A typ A max A typ A max
V min/max
0.001 1.0 150 300
5/16.5
VDD = 13.2 V Digital Inputs = 0 V or VDD Digital Inputs = 5 V
Gnd = 0V, Vss = 0V
1
Guaranteed by design, not subject to production test.
DUAL SUPPLY
VDD = 5 V 10%, VSS = -5 V 10%, GND = 0 V, unless otherwise noted. Table 3.
25C ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINLor IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1 Transition Time, tTRANS
tON (EN) tOFF (EN)
-40C to +85C
-40C to +125C 0 V to VDD
Unit V typ max typ max typ nA typ
Test Conditions/Comments
3 4 0.1
VS = 3.3V, IS = -10 mA; See figure x VDD = +4.5 V, VSS = -4.5 V VS = 3.3 V , IS = -10 mA
0.1 0.01 0.5 0.01 0.5 0.04 1 2.5 2.5 5 5 5 5 2.0 0.8 0.001 0.5 3 150 190
85 105 105 125 130 150
VS = -3 V/0 V/+3 V; IS = -10 mA VDD = +5.5 V, VSS = -5.5 V VS = 4.5 V, VD = 4.5 V; See figure x VS = 4.5 V, VD = 4.5 V; See figure x VS = VD = 4.5V; See figure x
nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max
ns typ ns max ns typ ns max
VIN = VINL or VINH
265
140 170
Break-Before-Make Time Delay, tD Charge Injection Off Isolation Channel-to-Channel Crosstalk
50 10 50 50 60
ns typ ns min pC typ dB typ dB typ
RL = 300 , CL = 35 pF VS = 3 V; Figure 25 RL = 300 , CL = 35 pF VS = 3 V; Figure 25 RL = 300 , CL = 35 pF VS = 3 V; Figure 25 RL = 300 , CL = 35 pF VS1 = VS2 = 3 V; See figure 25 VS = 0 V, RS = 0 , CL = 1 nF; See figure x RL = 50 , CL = 5 pF, f = 1 MHz; See figure x RL = 50 , CL = 5 pF, f = 1 MHz; See figure x
Rev. PrC| Page 5 of 17
ADG1436
25C 0.002 200 35 35 150 0.001 1.0 ISS
VDD/VSS
Preliminary Technical Data
-40C to +85C -40C to +125C Unit % typ MHz typ pF typ pF typ pF typ A typ A max A typ A max
V min/max
Total Harmonic Distortion + Noise -3 dB Bandwidth CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD
Test Conditions/Comments RL = 110, 5 V pp, f = 20 Hz to 20 kHz RL = 50 , CL = 5 pF; See figure x Vs = 0V, f = 1 MHz Vs = 0V, f = 1 MHz Vs = 0V, f = 1 MHz VDD = 5.5 V , Vss = -5.5V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD
Gnd = 0V
0.001 1.0
4.5/16.5
1
Guaranteed by design, not subject to production test.
Rev. PrC | Page 6 of 17
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 4.
Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, S or D Continuous Current, S or D Operating Temperature Range Automotive (Y Version) Storage Temperature Range Junction Temperature 16-Lead TSSOP, JA Thermal Impedance 16-Lead LFCSP, JA Thermal Impedance Reflow Soldering Peak Temperature, Pb free Ratings 35 V -0.3 V to +25 V +0.3 V to -25 V VSS - 0.3 V to VDD + 0.3 V GND - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 300 mA (pulsed at 1 ms, 10% duty cycle max) 200 mA -40C to +125C -65C to +150C 150C 150.4C/W 72.7C/W 260C
ADG1436
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1
Over voltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrC| Page 7 of 17
ADG1436 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Preliminary Technical Data
S1A IN1 NC NC
IN1 1 S1A 2 D1 3 S1B 4
16 15 14
NC NC NC
D1 1 S1B 2 Vss 3 Gnd 4
16 15 14 13 ADG1436
TOP VIEW (Not to Scale)
12 EN 11 Vdd 10 S2B 9 D2
ADG1236 13 VDD TOP VIEW VSS 5 (Not to Scale) 12 S2B
11 10 9
GND 6 NC 7 NC 8
D2 S2A IN2
04776-0-002
56
7
8
NC IN2 NC S2A
NC = NO CONNECT
EXPOSED PAD TIED TO SUBSTRATE, Vss NC = NO CONNECT
Figure 3.TSSOP Pin Configuration
Figure 4. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No. TSSOP LFCSP 1 15 2 16 3 1 4 2 5 3 6 4 7, 8, 14-16 5,7,13,14 9 6 10 8 11 9 12 10 13 11 12 Mnemonic IN1 S1A D1 S1B VSS GND NC IN2 S2A D2 S2B VDD EN Function Logic Control Input. Source Terminal. Can be an input or output. Drain Terminal. Can be an input or output. Source Terminal. Can be an input or output. Most Negative Power Supply Potential. Ground (0 V) Reference. No Connect. Logic Control Input. Source Terminal. Can be an input or output. Drain Terminal. Can be an input or output. Source Terminal. Can be an input or output. Most Positive Power Supply Potential. Active High Digital Input. When low, the device is disabled and all switches are off. When high, INx logic inputs determine the on switches.
TRUTH TABLE FOR SWITCHES
Table 6. ADG1436 TSSOP Truth Table
INx 0 1 Switch xA Off On Switch xB On Off
Table 7. ADG1436 LFCSPTruth Table
EN 0 1 1 INx X 0 1 SxA Off Off On SxB Off On Off
Rev. PrC | Page 8 of 17
Preliminary Technical Data TERMINOLOGY
IDD The positive supply current. ISS The negative supply current. VD (VS) The analog voltage on Terminals D and S. RON The ohmic resistance between D and S. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. ID (Off) The drain leakage current with the switch off. ID, IS (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic 0. VINH The minimum input voltage for Logic 1. IINL (IINH) The input current of the digital input. CS (Off) The off switch source capacitance, measured with reference to ground.
ADG1436
CD (Off) The off switch drain capacitance, measured with reference to ground. CD, CS (On) The on switch capacitance, measured with reference to ground. CIN The digital input capacitance. tTRANS The delay time between the 50% and 90% points of the digital input and switch on condition when switching from one address state to another. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental.
Rev. PrC| Page 9 of 17
ADG1436 TYPICAL PERFORMANCE CHARACTERISTICS
Preliminary Technical Data
Figure 5. On Resistance as a Function of VD (VS) for Dual Supply
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply
Figure 6, On Resistance as a Function of VD (VS) for Single l Supply
Figure 9. Leakage Current as a Function of VD (VS)
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures, Dual Supply Figure 10. Leakage Currents as a Function of VD (VS)
Rev. PrC | Page 10 of 17
Preliminary Technical Data
ADG1436
Figure 11. Leakage Current as a Function of VD (VS)
Figure 15. Charge Injection vs. Source Voltage Figure 12. Leakage Currents as a Function of Temperature
Figure 16. tTRANSITION Times vs. Temperature Figure 13. IDD vs. Logic Level
Figure 17. Off Isolation vs. Frequency Figure 14. Logic Threshold Voltage vs Supply Voltage
Rev. PrC| Page 11 of 17
ADG1436
Preliminary Technical Data
Figure 18. Crosstalk vs. Frequency
Figure 20. THD + N vs. Frequency
Figure 211. Capacitance vs. Source Voltage for Dual Supply Figure 222. Capacitance vs. Source Voltage for Single Supply
Figure 19. On Response vs. Frequency
Rev. PrC | Page 12 of 17
Preliminary Technical Data TEST CIRCUITS
V
IS (OFF) A
04776-0-020
ADG1436
S
D IDS
S
D
ID (OFF) A
04776-0-021
ID (ON) NC S D A VD
04776-0-022
VS
VS
VD
NC = NO CONNECT
Figure 23. On Resistance
Figure 24. Off Resistance
Figure 25. On Leakage
0.1F
VDD
VSS
0.1F
VIN
50%
50%
VDD VS SB SA IN VIN GND
VSS D RL 50 CL 35pF VOUT VIN 50% 90% 50% 90%
VOUT
tON
tOFF
Figure 26. Switching Times
0.1F
VDD
VSS
0.1F VIN
VDD VS SB SA IN VIN GND
VSS D RL 50 CL 35pF VOUT
VOUT
80%
tBBM
04776-0-023
tBBM
04776-0-024
Figure 27. Break-before-Make Time Delay
VDD 3V ENABLE DRIVE (VIN) 0V 50% 50% INx SA SB VS VDD VSS VSS
tON (EN)
0.9VO OUTPUT
tOFF (EN)
0.9VO VIN 50 EN GND D
OUTPUT 100 35pF
Figure 28. . Enable Delay, tON (EN), tOFF (EN)
Rev. PrC| Page 13 of 17
04861-025
ADG1436
0.1F VDD VSS 0.1F VIN (NORMALLY CLOSED SWITCH) NC VOUT CL 1nF VIN (NORMALLY OPEN SWITCH) VOUT VOUT
Preliminary Technical Data
VDD VS D
VSS SB SA
ON
OFF
IN VIN GND
Figure 29. Charge Injection
04776-0-025
QINJ = CL x VOUT
VDD 0.1F
VDD 0.1F VSS 0.1F NETWORK ANALYZER NC IN SA
D
VSS 0.1F
NETWORK ANALYZER VOUT RL 50
VDD SA
VSS
VDD
VSS
50
SB IN GND
D
R 50
SB
50 VS VOUT
04776-0-026
VS
VIN GND VOUT VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
VOUT VS
OFF ISOLATION = 20 LOG
Figure 32. Bandwidth
Figure 30. Off Isolation
VDD 0.1F
VSS 0.1F NETWORK ANALYZER NC 50
VDD 0.1F
VSS 0.1F AUDIO PRECISION RS S
VDD
VSS
VDD
VSS
IN
SA
SB
50 VS
IN D
D
VIN GND RL 50 VOUT
VIN
VS V p-p RL 600 VOUT
04776-0-029
GND
04776-0-027
INSERTION LOSS = 20 LOG
VOUT WITH SWITCH VOUT WITHOUT SWITCH
Figure 33. THD + Noise
Figure 31. Channel-to-Channel Crosstalk
Rev. PrC | Page 14 of 17
04776-0-028
RL 50
Preliminary Technical Data OUTLINE DIMENSIONS
5.10 5.00 4.90
ADG1436
16
9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 0.15 0.05 0.65 BSC 0.30 0.19 COPLANARITY 0.10 1.20 MAX
0.20 0.09
SEATING PLANE
8 0
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153AB
Figure 34. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in inches and (millimeters
4.00 BSC SQ
0.60 MAX 0.60 MAX 0.65 BSC 3.75 BSC SQ 0.75 0.60 0.50
13 12 16 1
PIN 1 INDICATOR 2.25 2.10 SQ 1.95 0.25 MIN 1.95 BSC
PIN 1 INDICATOR
TOP VIEW
(BOTTOM VIEW)
EXPOSED PAD
4 5
9
8
12 MAX 1.00 0.85 0.80
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 35. 16-Lead Lead Frame Chip Scale Package [VQ_LFCSP] 4 mm x 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters
ORDERING GUIDE
Model ADG1436YRUZ ADG1436YRUZREEL ADG1436YRUZREEL7 ADG1436YCPZ500RL7 ADG1436YCPZREEL7 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Lead Frame Chip Scale Package (LFCSP) Lead Frame Chip Scale Package (LFCSP) Package Option RU-16 RU-16 RU-16 CP-16-4 CP-16-4
Rev. PrC| Page 15 of 17
ADG1436 NOTES
Preliminary Technical Data
Rev. PrC | Page 16 of 17
Preliminary Technical Data NOTES
ADG1436
(c) 2007Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06817-0-5/07(PrC)
Rev. PrC| Page 17 of 17

▲Up To Search▲

Price & Availability of ADG1436

	To Download ADG1436 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .